ST7DALIF2 datasheet(131/171 Pages) STMICROELECTRONICS

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ST7DALIF2

Electrical characteristics

131/171

20.3.1

Operating conditions with low voltage detector (LVD)

TA = -40 to 85°C, unless otherwise specified

20.3.2

Auxiliary Voltage Detector (AVD) Thresholds

TA = -40 to 85°C, unless otherwise specified

20.3.3

Internal RC oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by

option byte).

Table 66.

Power on/power down operating conditions

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIT+(LVD)

Reset release threshold

(VDD rise)

High Threshold

Med. Threshold

Low Threshold

4.00(1)

3.40 (1)

2.65 (1)

Not tested in production.

4.25

3.60

2.90

4.50

3.80

3.15

VIT-(LVD)

Reset generation threshold

(VDD fall)

High Threshold

Med. Threshold

Low Threshold

3.80

3.20

2.40

4.05

3.40

2.70

4.30 (1)

3.65 (1)

2.90(1)

Vhys

LVD voltage threshold

hysteresis

VIT+(LVD)-VIT-(LVD)

200

VtPOR

VDD rise time rate

(2)(3)

Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on

and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the

MCU.

Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the

application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit

example in Figure 87 on page 150 and note 4.

20000

μs/V

tg(VDD)

Filtered glitch delay on VDD

Not detected by the

LVD

150

IDD(LVD) LVD/AVD current consumption

220

μA

Table 67.

AVD thresholds

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIT+(AVD)

1=>0 AVDF flag toggle

threshold

(VDD rise)

High Threshold

Med. Threshold

Low Threshold

4.40(1)

3.90(1)

3.20(1)

Not tested in production.

4.70

4.10

3.40

5.00

4.30

3.60

VIT-(AVD)

0=>1 AVDF flag toggle

threshold

(VDD fall)

High Threshold

Med. Threshold

Low Threshold

4.30

3.70

2.90

4.60

3.90

3.20

4.90(1)

4.10(1)

3.40(1)

Vhys

AVD voltage threshold

hysteresis

VIT+(AVD)-VIT-(AVD)

150

ΔV

IT-

Voltage drop between AVD

flag set and LVD reset

activation

VDD fall

0.45

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