ST7DALIF2 datasheet(133/171 Pages) STMICROELECTRONICS

133 / 171 page

ST7DALIF2

Electrical characteristics

133/171

Table 70.

RC oscillator and PLL characteristics (tested for TA = -40 to +85° C) @ VDD = 2.7 to

3.3 V

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fRC

(1)

Internal RC oscillator

frequency

RCCR = FF (reset value), TA=25°C,

VDD= 3.0 V

560

kHz

RCCR=RCCR1(2) ,TA=25° C, VDD= 3 V

700

ACCRC

Accuracy of Internal RC

oscillator when

calibrated with

RCCR=RCCR1(3)(2)

TA=25° C,VDD=3 V

-2

TA=25° C,VDD=2.7 to 3.3 V

-25

+25

TA=-40 to +85°C, VDD=3 V

-15

IDD(RC)

RC oscillator current

consumption

TA=25° C,VDD=3 V

700(3)

μA

tsu(RC)

RC oscillator setup time

TA=25° C,VDD=3 V

10(2)

μs

fPLL

x4 PLL input clock

0.7(3)

MHz

tLOCK

PLL Lock time(4)

2ms

tSTAB

PLL Stabilization time(4)

4ms

ACCPLL

x4 PLL Accuracy

fRC = 1 MHz@TA=25° C, VDD=2.7 to 3.3 V

0.1(5)

fRC = 1 MHz@TA=40 to +85°C, VDD= 3 V

0.1(5)

tw(JIT)

PLL jitter period

fRC = 1 MHz

125(6)

µs

JITPLL

PLL jitter (

Δf

CPU/fCPU)1

(6)

IDD(PLL)

PLL current

consumption

TA=25° C

190(3)

μA

If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor,

typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.

See Section 9.2: Internal RC oscillator adjustment on page 32.

Data based on characterization results, not tested in production

After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 11 on page 34.

Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy

Guaranteed by design.

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