ST7DALIF2 datasheet(151/171 Pages) STMICROELECTRONICS

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ST7DALIF2

Electrical characteristics

151/171

RESET pin protection when LVD is disabled

When the LVD is disabled, it is recommended to protect the RESET pin as shown in

Figure 88 and follow these guidelines:

The reset network protects the device against parasitic resets.

The output of the external reset circuit must have an open-drain output to drive the ST7

reset pad. Otherwise the device can be damaged when the ST7 generates an internal

reset (LVD or watchdog).

Whatever the reset source is (internal or external), the user must ensure that the level

on the RESET pin can go below the VIL max. level specified in Section 20.8. Otherwise

the reset will not be taken into account internally.

Because the reset circuit is designed to allow the internal RESET to be output in the

RESET pin, the user must ensure that the current sunk on the RESET pin (by an

external pull-up for example) is less than the absolute maximum value specified for

IINJ(RESET) in Section 20.2 on page 128.

Figure 88.

RESET pin protection when LVD is disabled.

20.10

Communication interface characteristics

20.10.1

SPI - serial peripheral interface

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (SS, SCK, MOSI, MISO).

0.01

μF

EXTERNAL

RESET

CIRCUIT

USER

Required

ST72XXX

PULSE

GENERATOR

Filter

RON

VDD

INTERNAL

RESET

WATCHDOG

ILLEGAL OPCODE

Table 88.

SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK =

1/tc(SCK)

SPI clock frequency

Master

fCPU=8 MHz fCPU/128 =0.0625

fCPU/4 =2

MHz

Slave

fCPU=8 MHz

fCPU/2 =4

tr(SCK)

tf(SCK)

SPI clock rise and fall

time

see I/O port pin description

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