ST7LITE49K2 datasheet(205/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

Electrical characteristics

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13.5.2

SPI interface

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (SS, SCK, MOSI, MISO).

Table 82.

SPI interface characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master

fCPU=8 MHz

fCPU/128

0.0625

fCPU/4

MHz

Slave

fCPU=8 MHz

fCPU/2

tr(SCK)

tf(SCK)

SPI clock rise and fall time

see I/O port pin description

tsu(SS)

(1)

Data based on design simulation, not tested in production.

SS setup time (2)

Depends on fCPU. For example, if fCPU = 8 MHz, then TCPU = 1/fCPU =125 ns and tsu(SS)= 550 ns

Slave

(4 x TCPU) + 50

th(SS)

(1)

SS hold time

Slave

120

tw(SCKH)

(1)

tw(SCKL)

(1)

SCK high and low time

Master

Slave

100

tsu(MI)

(1)

tsu(SI)

(1)

Data input setup time

Master

Slave

100

th(MI)

(1)

th(SI)

(1)

Data input hold time

Master

Slave

100

ta(SO)

(1)

Data output access time

Slave

120

tdis(SO)

(1)

Data output disable time

Slave

240

tv(SO)

(1)

Data output valid time

Slave (after

enable edge)

120

th(SO)

(1)

Data output hold time

tv(MO)

(1)

Data output valid time

Master (after

enable edge)

120

th(MO)

(1)

Data output hold time

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