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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST7LITE49K2 데이터시트(PDF) 207 Page - STMicroelectronics |
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ST7LITE49K2 데이터시트(HTML) 207 Page - STMicroelectronics |
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207 / 245 page  ST7LITE49K2 Electrical characteristics 207/245 Figure 97. SPI master timing diagram 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration. 13.6 Clock and timing characteristics Subject to general operating conditions for VDD, fOSC, and TA. SS INPUT CPHA = 0 MOSI OUTPUT MISO INPUT CPHA = 0 CPHA = 1 CPHA = 1 tc(SCK) tw(SCKH) tw(SCKL) th(MI) tsu(MI) MSB IN MSB OUT BIT6 IN BIT6 OUT LSB OUT LSB IN See note 2 Seenote2 CPOL = 0 CPOL = 1 CPOL = 0 CPOL = 1 tr(SCK) tf(SCK) th(MO) tv(MO) Table 83. General timings Symbol Parameter(1) 1. Guaranteed by Design. Not tested in production. Conditions Min Typ(2) 2. Data based on typical application software. Max Unit tc(INST) Instruction cycle time fCPU = 8 MHz 23 12 tCPU 250 375 1500 ns tv(IT) Interrupt reaction time(3) tv(IT) = Δtc(INST) + 10 3. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles needed to finish the current instruction execution. fCPU = 8 MHz 10 22 tCPU 1.25 2.75 μs |
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