ST7LITE49K2 datasheet(230/245 Pages) STMICROELECTRONICS

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Device configuration and ordering information

ST7LITE49K2

230/245

Device configuration and ordering information

This device is available for production in user programmable version (Flash).

ST7LITE49K2 XFlash devices are shipped to customers with a default program memory

content (FFh).

14.1

Option bytes

The two option bytes allow the hardware configuration of the microcontroller to be selected.

The option bytes can be accessed only in programming mode (for example using a standard

ST7 programming tool).

14.1.1

Option byte 1

Bits 7:6 = CKSEL[1:0] Start-up clock selection.

These bits are used to select the startup frequency. By default, the internal RC is

selected.

Bit 5 = Reserved, must always be 1.

Bit 4 = PLL32OFF 32 MHz PLL disabled.

0: PLL32 enabled

1: PLL32 disabled (by-passed). By default the PLL32 is disabled.

Bits 3:2 = LVD[1:0] Low voltage detection selection.

These option bits enable the low voltage detection block (LVD) with a selected

threshold as shown in Table 107.

Table 106.

Startup clock selection

Configuration

CKSEL1

CKSEL0

Internal RC as startup clock

AWU RC as a startup clock

External crystal/ceramic resonator

External clock

Table 107.

LVD threshold configuration

Configuration

VD1

VD0

LVD Off (default value)

Highest voltage threshold

Medium voltage threshold

Lowest voltage threshold

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