ST72361J4-Auto datasheet(59/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

Interrupts

Doc ID 12468 Rev 3

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These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bits 1:0 = IS0[1:0] ei0 sensitivity

The interrupt sensitivity, defined using the IS0[1:0] bits, is applied to the ei0 external

interrupts:

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

External Interrupt Control Register 1 (EICR1)

Read/Write

Reset value: 0000 0000 (00h)

BIts 7:2 = Reserved

Bit 1 = TLIS Top Level Interrupt sensitivity

This bit configures the TLI edge sensitivity. It can be set and cleared by software only when

TLIE bit is cleared.

0: Falling edge

1: Rising edge

Bit 0 = TLIE Top Level Interrupt enable

This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and

cleared by software.

0: TLI disabled

1: TLI enabled

Note:

A parasitic interrupt can be generated when clearing the TLIE bit.

In some packages, the TLI pin is not available. In this case, the TLIE bit must be kept low to

avoid parasitic TLI interrupts.

Falling edge only

Rising and falling edge

Table 20.

Interrupt sensitivity - ei0

IS01

IS00

External interrupt sensitivity

Falling edge and low level

Rising edge only

Falling edge only

Rising and falling edge

TLIS

TLIE

Table 19.

Interrupt sensitivity - ei1

IS11

IS10

External interrupt sensitivity

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