ST72361J4-Auto datasheet(82/279 Pages) STMICROELECTRONICS

부품명	ST72361J4-Auto

상세설명	Clock, reset and supply management

PDF	279 Pages

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Window watchdog (WWDG)

ST72361xx-Auto

82/279

Doc ID 12468 Rev 3

9.4

Using halt mode with the WDG

If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT

instruction), it is recommended before executing the HALT instruction to refresh the WDG

counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

9.5

How to program the watchdog timeout

Figure 35 shows the linear relationship between the 6-bit value to be loaded in the

Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be

used for a quick calculation without taking the timing variations into account. If more

precision is needed, use the formulae in Figure 36.

Caution:

When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 35.

Approximate timeout duration

Watchdog timeout (ms) @ 8 MHz fOSC2

128

1.5

114

ST72361J4-Auto 데이터시트(PDF) 82 Page - STMicroelectronics