ST72361AR4-Auto datasheet(217/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

10-bit A/D converter (ADC)

Doc ID 12468 Rev 3

217/279

Bit 7 = EOC End of Conversion

This bit is set by hardware. It is cleared by software reading the ADCDRH register or writing

to any bit of the ADCCSR register.

0: conversion is not complete

1: conversion complete

Bit 6 = SPEED A/D clock selection

This bit is set and cleared by software.

Bit 5 = ADON A/D Converter on

This bit is set and cleared by software.

0: disable ADC and stop conversion

1: enable ADC and start conversion

Bit 4 = SLOW A/D Clock Selection

This bit is set and cleared by software. It works together with the SPEED bit. Refer to

Table 91.

Bits 3:0 = CH[3:0] Channel Selection

These bits are set and cleared by software. They select the analog input to convert.

Table 83.

A/D clock selection

fADC

Slow

Speed

fCPU/2

fCPU (where fCPU <= 4 MHz)

fCPU/4

fCPU/2 (same frequency as SLOW = 0, SPEED = 0)

Table 84.

ADC channel selection

Channel pin(1)

CH3

CH2

CH1

CH0

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

ST72361AR4-Auto 데이터시트(PDF) 217 Page - STMicroelectronics

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