ST72361AR4-Auto datasheet(220/279 Pages) STMICROELECTRONICS

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Instruction set

ST72361xx-Auto

220/279

Doc ID 12468 Rev 3

18.1.1

Inherent

All Inherent instructions consist of a single byte. The opcode fully specifies all the required

information for the CPU to process the operation.

Short

Indirect Indexed ld A, ([$10],X)

00..1FE

00..FF

byte

+ 2

Long

Indirect Indexed ld A, ([$10.w], X)

0000..FFFF

00..FF

word

+ 2

Relative

Direct

jrne loop

PC+/-127

+ 1

Relative

Indirect

jrne [$10]

PC+/-127

00..FF

byte

+ 2

Bit

Direct

bset $10, #7

00..FF

+ 1

Bit

Indirect

bset [$10], #7

00..FF

byte

+ 2

Bit

Direct

Relative btjt $10,#7, skip

00..FF

+ 2

Bit

Indirect Relative btjt [$10],#7, skip

00..FF

byte

+ 3

Table 87.

CPU addressing mode overview (continued)

Mode

Syntax

Destination

Pointer

address

(hex.)

Pointer

size

(hex.)

Length

(bytes)

Inherent instruction

Function

NOP

No operation

TRAP

S/W interrupt

WFI

Wait for interrupt (low power mode)

HALT

Halt oscillator (lowest power mode)

RET

Sub-routine return

IRET

Interrupt sub-routine return

SIM

Set interrupt mask (level 3)

RIM

Reset interrupt mask (level 0)

SCF

Set carry flag

RCF

Reset carry flag

RSP

Reset stack pointer

Load

CLR

Clear

PUSH/POP

Push/pop to/from the stack

INC/DEC

Increment/decrement

TNZ

Test negative or zero

CPL, NEG

1 or 2 complement

MUL

Byte multiplication

SLL, SRL, SRA, RLC, RRC

Shift and rotate operations

SWAP

Swap nibbles

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