ST72561J4-Auto datasheet(240/324 Pages) STMICROELECTRONICS

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beCAN controller (beCAN)

ST72561-Auto

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Doc ID 12370 Rev 8

corresponding interrupt in the CEIER is enabled. Setting this bit generates a status change

interrupt if the ERRIE bit in the CIER register is set.

This bit is cleared by software.

Bit 1 = SLAK Sleep Acknowledge

Read

This bit is set by hardware and indicates to the software that the CAN hardware is now in

sleep mode. This bit acknowledges the sleep mode request from the software (set SLEEP

bit in CMCR register).

This bit is cleared by hardware when the CAN hardware has left sleep mode. Sleep mode is

left when the SLEEP bit in the CMCR register is cleared. Please refer to the AWUM bit of the

CMCR register description for detailed information for clearing SLEEP bit.

Bit 0 = INAK Initialization Acknowledge

Read

This bit is set by hardware and indicates to the software that the CAN hardware is now in

initialization mode. This bit acknowledges the initialization request from the software (set

INRQ bit in CMCR register).

This bit is cleared by hardware when the CAN hardware has left the initialization mode and

is now synchronized on the CAN bus. To be synchronized the hardware has to monitor a

sequence of 11 consecutive recessive bits on the CAN RX signal.

17.8.2

CAN transmit status register (CTSR)

Read/ write

Reset value: 0000 0000 (00h)

Note:

To clear a bit of this register the software must write this bit with a one.

Bits 7:6 = reserved. Forced to 0 by hardware.

Bit 5 = TXOK1 Transmission OK for mailbox 1

Read

This bit is set by hardware when the transmission request on mailbox 1 has been completed

successfully. Please refer to Figure 100.

This bit is cleared by hardware when mailbox 1 is requested for transmission or when the

software clears the RQCP1 bit.

Bit 4 = TXOK0 Transmission OK for mailbox 0

Read

This bit is set by hardware when the transmission request on mailbox 0 has been completed

successfully. Please refer to Figure 100.

This bit is cleared by hardware when mailbox 0 is requested for transmission or when the

software clears the RQCP0 bit.

Bits 3:2 = reserved. Forced to 0 by hardware.

Bit 1 = RQCP1 Request Completed for Mailbox 1

Read/ clear

TXOK1

TXOK0

RQCP1

RQCP0

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