ST72561J4-Auto datasheet(244/324 Pages) STMICROELECTRONICS

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beCAN controller (beCAN)

ST72561-Auto

244/324

Doc ID 12370 Rev 8

Bit 3 = reserved. Forced to 0 by hardware.

Bit 2 = BOFF Bus-Off Flag

Read

This bit is set by hardware when it enters the bus-off state. The bus-off state is entered on

TECR overrun, TEC greater than 255, refer to Error management.

Bit 1 = EPVF Error Passive Flag

Read

This bit is set by hardware when the error passive limit has been reached (receive error

counter or transmit error counter greater than 127).

Bit 1 = EWGF Error Warning Flag

Read

This bit is set by hardware when the warning limit has been reached. Receive error counter

or transmit error counter greater than 96.

CAN error interrupt enable register (CEIER)

Read/ write

Reset value: 0000 0000 (00h)

Note:

All bits of this register are set and clear by software.

Bit 7 = ERRIE Error Interrupt Enable

0: no interrupt will be generated when an error condition is pending in the CESR.

1: an interrupt will be generation when an error condition is pending in the CESR.

Bits 6:5 = reserved. Forced to 0 by hardware.

Bit 4 = LECIE Last Error Code Interrupt Enable

0: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error

detection.

1: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error

detection.

Bit 3 = reserved. Forced to 0 by hardware.

Bit 2 = BOFIE Bus-Off Interrupt Enable

0: ERRI bit will not be set when BOFF is set.

1: ERRI bit will be set when BOFF is set.

Bit 1 = EPVIE Error Passive Interrupt Enable

0: ERRI bit will not be set when EPVF is set.

1: ERRI bit will be set when EPVF is set.

Bit 0 = EWGIE Error Warning Interrupt Enable

0: ERRI bit will not be set when EWGF is set.

1: ERRI bit will be set when EWGF is set.

ERRIE

LECIE

BOFIE

EPVIE

EWGIE

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