ST72561J4-Auto datasheet(241/324 Pages) STMICROELECTRONICS

241 / 324 page

ST72561-Auto

beCAN controller (beCAN)

Doc ID 12370 Rev 8

241/324

This bit is set by hardware to signal that the last request for mailbox 1 has been completed.

The request could be a transmit or an abort request.

This bit is cleared by software.

Bit 0 = RQCP0 Request Completed for Mailbox 0

Read/ clear

This bit is set by hardware to signal that the last request for mailbox 0 has been completed.

The request could be a transmit or an abort request.

This bit is cleared by software.

CAN transmit priority register (CTPR)

All bits of this register are read only.

Reset value: 0000 1100 (0Ch)

Bit 7 = reserved. Forced to 0 by hardware.

Bit 6 = LOW1 Lowest Priority Flag for Mailbox 1

Read

This bit is set by hardware when more than one mailbox are pending for transmission and

mailbox 1 has the lowest priority.

Bit 5 = LOW0 Lowest Priority Flag for Mailbox 0

Read

This bit is set by hardware when more than one mailbox are pending for transmission and

mailbox 0 has the lowest priority.

Note:

These bits are set to zero when only one mailbox is pending.

Bit 4 = Reserved. Forced to 0 by hardware.

Bit 3 = TME1 Transmit Mailbox 1 Empty

Read

This bit is set by hardware when no transmit request is pending for mailbox 1.

Bit 2 = TME0 Transmit Mailbox 0 Empty

Read

This bit is set by hardware when no transmit request is pending for mailbox 0.

Bit 1:0 = CODE Mailbox Code

Read

In case at least one transmit mailbox is free, the code value is equal to the number of the

next transmit mailbox free.

In case all transmit mailboxes are pending, the code value is equal to the number of the

transmit mailbox with the lowest priority.

LOW1

LOW0

TME1

TME0

CODE

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