ST72361AR6-Auto datasheet(63/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

Power saving modes

Doc ID 12468 Rev 3

63/279

Figure 24.

WAIT mode flow-chart

Note:

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the

CC register are set to the current software priority level of the interrupt routine and

recovered when the CC register is popped.

7.4

Halt mode

The HALT mode is the lowest power consumption mode of the MCU. It is entered by

executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status

MCC/RTC for more details on the MCCSR register) and when the AWUEN bit in the

AWUCSR register is cleared.

The MCU can exit HALT mode on reception of either a specific interrupt (see Table 16) or a

RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is

immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the

oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or

by fetching the reset vector which woke it up (see Figure 26).

When entering HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable

interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In HALT mode, the main oscillator is turned off causing all internal processing to be stopped,

including the operation of the on-chip peripherals. All peripherals are not clocked except the

ones which get their clock supply from another clock generator (such as an external or

auxiliary oscillator).

The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT”

option bit of the option byte. The HALT instruction when executed while the Watchdog

WFI INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 1)

256 OR 4096 CPU CLOCK

CYCLE DELAY

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