ST72561AR4-Auto datasheet(91/324 Pages) STMICROELECTRONICS

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ST72561-Auto

Main clock controller with real time clock MCC/RTC

Doc ID 12370 Rev 8

91/324

Bit 4 = SMS Slow mode select

This bit is set and cleared by software.

0: Normal mode. fCPU = fOSC2

1: Slow mode. fCPU is given by CP1, CP0

See Section 7.2: Slow mode and Section 10: Main clock controller with real time clock

MCC/RTC for more details.

Bits 3:2 = TB[1:0] Time base control

These bits select the programmable divider time base. They are set and cleared by

software.

A modification of the time base is taken into account at the end of the current period

(previously set) to avoid an unwanted time shift. This allows to use this time base as a real

time clock.

Bit 1 = OIE Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

1: Oscillator interrupt enabled

This interrupt can be used to exit from ACTIVE HALT mode.

When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE HALT

power saving mode.

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software reading the CSR register. It indicates

when set that the main oscillator has reached the selected elapsed time (TB1:0).

0: Timeout not reached

1: Timeout reached

Table 40.

CPU clock frequency in SLOW mode

fCPU in SLOW mode

CP1

CP0

fOSC2 / 2

fOSC2 / 4

fOSC2/ 8

fOSC2 / 16

Table 41.

Time base selection

Counter prescaler

Time base

TB1

TB0

fOSC2 =4 MHz

fOSC2 =8 MHz

16000

4ms

2ms

32000

8ms

4ms

80000

20ms

10ms

200000

50ms

25ms

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