STM32L162RC datasheet(24/123 Pages) STMICROELECTRONICS

24 / 123 page

Functional overview

STM32L162VC, STM32L162RC

24/123

DocID022881 Rev 10

3.9

LCD (liquid crystal display)

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320

pixels.

•

Internal step-up converter to guarantee functionality and contrast control irrespective of

VDD. This converter can be deactivated, in which case the VLCD pin is used to provide

the voltage to the LCD

•

Supports static, 1/2, 1/3, 1/4 and 1/8 duty

•

Supports static, 1/2, 1/3 and 1/4 bias

•

Phase inversion to reduce power consumption and EMI

•

Up to 8 pixels can be programmed to blink

•

Unneeded segments and common pins can be used as general I/O pins

•

LCD RAM can be updated at any time owing to a double-buffer

•

The LCD controller can operate in Stop mode

•

VLCD rail decoupling capability

3.10

ADC (analog-to-digital converter)

A 12-bit analog-to-digital converters is embedded into STM32L162xC devices with up to 25

external channels, performing conversions in single-shot or scan mode. In scan mode,

automatic conversion is performed on a selected group of analog inputs with up to 24

external channels in a group.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all scanned channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to

the ADC start triggers, to allow the application to synchronize A/D conversions and timers.

An injection mode allows high priority conversions to be done by interrupting a scan mode

which runs in as a background task.

The ADC includes a specific low-power mode. The converter is able to operate at maximum

speed even if the CPU is operating at a very low frequency and has an auto-shutdown

function. The ADC’s runtime and analog front-end current consumption are thus minimized

whatever the MCU operating mode.

Table 6. VLCD rail decoupling

Bias

1/2

1/3

1/4

VLCDRAIL1

1/2 VLCD

2/3 VLCD

1/2 VLCD

PB2

VLCDRAIL2

N/A

1/3 VLCD

1/4 VLCD

PB12

PE11

VLCDRAIL3

N/A

3/4 VLCD

PB0

PE12

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