STM32F769AI datasheet(148/255 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

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DocID029041 Rev 4

Table 48. PLLI2S characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPLLI2S_IN

PLLI2S input clock(1)

0.95(2)

2.10

MHz

fPLLI2SP_OUT

PLLI2S multiplier output clock for

SPDIFRX

216

fPLLI2SQ_OUT

PLLI2S multiplier output clock for

SAI

216

fPLLI2SR_OUT

PLLI2S multiplier output clock for

I2S

216

fVCO_OUT

PLLI2S VCO output

100

432

tLOCK

PLLI2S lock time

VCO freq = 192 MHz

200

μs

VCO freq = 432 MHz

100

300

Jitter(3)

Master I2S clock jitter

Cycle to cycle at

12.288 MHz on

48KHz period,

N=432, R=5

RMS

peak

±280

Average frequency of

12.288 MHz

N = 432, R = 5

on 1000 samples

-90

WS I2S clock jitter

Cycle to cycle at 48 KHz

on 1000 samples

400

IDD(PLLI2S)(4)

PLLI2S power consumption on

VDD

VCO freq = 192 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLLI2S)(4)

PLLI2S power consumption on

VDDA

VCO freq = 192 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed by characterization results.

Table 49. PLLISAI characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPLLSAI_IN

PLLSAI input clock(1)

0.95(2)

2.10

MHz

fPLLSAIP_OUT

PLLSAI multiplier output clock

for 48 MHz

fPLLSAIQ_OUT

PLLSAI multiplier output clock

for SAI

216

fPLLSAIR_OUT

PLLSAI multiplier output clock

for LCD-TFT

216

fVCO_OUT

PLLSAI VCO output

100

432

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