STM32F769AI datasheet(152/255 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

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DocID029041 Rev 4

VIL

Output low level voltage

1.1

1.2

VIL-ULPS

Output high level voltage

-50

VIH

Output impedance of LP

transmitter

-110

Vhys

15%-85% rise and fall time

LP Contention Detector Characteristics

VILCD

Logic 0 contention threshold

200

VIHCD

Logic 0 contention threshold

450

1. Guaranteed based on test during characterization.

Table 52. MIPI D-PHY AC characteristics LP mode and HS/LP

transitions(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TLPX

Transmitted length of any Low-

Power state period

-50

TCLK-PREPARE

Time that the transmitter drives

the Clock Lane LP-00 Line

state immediately before the

HS-0 Line state starting the HS

transmission.

-38

TCLK-PREPARE

TCLK-ZERO

Time that the transmitter drives

the HS-0 state prior to starting

the clock.

300

TCLK-PRE

Time that the HS clock shall be

driven by the transmitter prior to

any associated Data Lane

beginning the transition from

LP to HS mode.

-8

Table 51. MIPI D-PHY characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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