CS5372 datasheet(14/22 Pages) CIRRUS

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CS5371/CS5372

DS255PP2

7%. The one’s density of the MDATA output is de-

fined as the ratio of ‘1’ bits to total bits in the serial

bitstream output, i.e. an 86% one’s density has, on

average, a ‘1’ value in 86 of every 100 output data

bits.

When operated with the CS5376 digital filter, the

full scale

24-bit

output codes

range

from

0x5FFFFF (decimal 6,291,455) to 0xA00001 (dec-

imal -6,291,455).

Note that for a full scale input signal, 5 Vp-p

(2.5 Vdiff) with VREF=2.5 V, the CS5371/CS5372

and CS5376 chip set does not output a maximum

24-bit 2’s complement digital code of 0x7FFFFF

(digital 8,388,607), but instead a lower scaled value

to allow over-range capability. The CS5376 con-

verts to full performance specification up to a pos-

itive over-range value of 0x64CCCC (decimal

6,606,028) and down to a negative over-range val-

ue of 0x9B3334 (decimal -6,606,028).

7.3.

Modulator Sync - MSYNC

To synchronize the analog sampling instant and

timing of the digital output bitstream, the

CS5371/CS5372 modulators use an MSYNC sig-

nal. When using the CS5376 digital filter, MSYNC

is automatically generated from a SYNC signal in-

put from the external system.

The MSYNC input is rising edge triggered and re-

sets the internal MCLK counter-divider so the ana-

log sampling instant occurs during a consistent

MCLK phase. It also sets the MDATA output tim-

ing so the bitstream can be properly sampled by the

CS5376 digital filter input.

7.4.

Modulator Flag - MFLAG

The CS5371/CS5372 modulators are 4th order

∆−

Σ and are therefore conditionally stable. The mod-

ulators may go into an oscillatory condition if the

analog inputs are over-ranged more than 5% past

either positive or negative full scale.

If an unstable condition is detected, the modulators

collapse to a 1st order system until loop stability is

achieved. During this time, the MFLAG pin tran-

sitions from low to high to signal an error condi-

tion. The analog input signal must be reduced to

within the full scale range for at least 32 MCLK cy-

cles for the modulator to recover from an unstable

condition.

The MFLAG output connects to a dedicated input

on the CS5376 digital filter, causing an error bit to

be set in the status portion of the digital output data

word when detected.

8. POWER MODES

Four power modes are available when using the

CS5371/CS5372 modulators. Normal power and

low power modes are operational modes, power

down and micro power modes are non-operational

standby modes.

8.1.

Normal Power Mode

The normal operational mode for the modulators,

LPWR=0 and MCLK=2.048 MHz, provides the

best performance with power consumption of

25 mW per channel. This power mode is recom-

mended when maximum conversion accuracy is re-

quired.

Table 1. Output coding for the CS5371/CS5372 and

CS5376 combination

Modulator Input

Signal

CS5376 Filter

Output Code

HEX

Decimal

> + (VREF + 5%)

Error Flag Possible

≈ + (VREF + 5%)

64CCCC

+6606028

+VREF

5FFFFF

+6291455

000000

-VREF

A00001

-6291455

≈ - (VREF + 5%)

9B3334

-6606028

> - (VREF + 5%)

Error Flag Possible

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