| 전자부품 데이터시트 검색엔진 |
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CS5531-AS 데이터시트(PDF) 27 Page - Cirrus Logic |
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CS5531-AS 데이터시트(HTML) 27 Page - Cirrus Logic |
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27 / 52 page ![]() CS5531/32/33/34 DS289PP5 27 to limit drive currents to less than 20 µA to reduce self-heating of the chip. These outputs are powered from VA+ and VA-. Their output voltage will be limited to the VA+ voltage for a logic 1 and VA- for a logic 0. 2.3.7. Offset and Gain Select The Offset and Gain Select bit (OGS) is used to se- lect the source of the calibration registers to use when performing conversions and calibrations. When the OGS bit is set to ‘0’, the offset and gain registers corresponding to the desired physical channel (CS1-CS0 in the selected Setup) will be ac- cessed. When the OGS bit is set to ‘1’, the offset and gain registers pointed to by the OG1-OG0 bits in the selected Setup will be accessed. This feature allows multiple calibration values (e.g. for different gain settings) to be used on a single physical chan- nel without having to re-calibrate or manipulate the calibration registers. 2.3.8. Filter Rate Select The Filter Rate Select bit (FRS) modifies the output word rates of the converter to allow either 50 Hz or 60 Hz rejection when operating from a 4.9152 MHz crystal. If FRS is cleared to logic 0, the word rates and corresponding filter characteristics can be selected (using the Channel Setup Registers) from 7.5, 15, 30, 60, 120, 240, 480, 960, 1920, or 3840 Sps when using a 4.9152 MHz clock. If FRS is set to logic 1, the word rates and corresponding filter characteristics scale by a factor of 5/6, making the selectable word rates 6.25, 12.5, 25, 50, 100, 200, 400, 800, 1600, and 3200 Sps when using a 4.9152 MHz clock. When using other clock frequencies, these selectable word rates will scale linearly with the clock frequency that is used. VR E F C = 22pF f= 2 φ Fine 1 V ≤ 15 m V i= fV C os os n φ Coarse MCLK 16 VRS = 1; 1 V ≤ V ≤ 2.5 V REF Figure 9. Input Reference Model when VRS = 1 VR EF C= 1 1p F f= 2 φ Fine 1 V ≤ 30 m V i= fV C os os n φ C oarse MCLK 16 VRS = 0; 2.5 V < V ≤ VA+ REF Figure 10. Input Reference Model when VRS = 0 |
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