AS4C64M32MD2-25BCN datasheet(27/129 Pages) ALSC

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4.4 Burst Read Command

The Burst Read command is initiated by having CS# LOW, CA0 HIGH, CA1 LOW and CA2 HIGH at the rising edge of

the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for

the burst. The Read Latency (RL) is defined from the rising edge of the clock on which the Read Command is issued

to the rising edge of the clock from which the tDQSCK delay is measured. The first valid datum is available RL * tCK +

tDQSCK + tDQSQ after the rising edge of the clock where the Read Command is issued. The data strobe output is

driven LOW tRPRE before the first rising valid strobe edge. The first bit of the burst is synchronized with the first rising

edge of the data strobe. Each subsequent data-out appears on each DQ pin edge aligned with the data strobe. The

RL is programmed in the mode registers.

Timings for the data strobe are measured relative to the crosspoint of DQS and its complement, DQS#.

CK#

DQS#

DQS

RL-1

RL+BL/2

tCH

tCL

tLZ(DQS)

tRPRE

tDQSCKmax

tRPST

tHZ(DQS)

DOUT

tQH

tDQSQmax

tQH

tDQSQmax

tHZ(DQ)

tLZ(DQ)

Transitioning data

Figure 4.4 — Data output (read) timing (tDQSCKmax)

NOTE 1 tDQSCK may span multiple clock periods.

NOTE 2 An effective Burst Length of 4 is shown.

CK#

DQS#

DQS

RL-1

RL+BL/2

tCH

tCL

tRPRE

tDQSCKmin

tRPST

tHZ(DQS)

DOUT

tQH

tDQSQmax

tQH

tDQSQmax

tHZ(DQ)

tLZ(DQ)

tLZ(DQS)

Transitioning data

Figure 4.5 — Data output (read) timing (tDQSCKmin)

NOTE 1 An effective Burst Length of 4 is shown.

AS4C64M32MD2-25BCN

AS4C128M16MD2-25BCN

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Rev.1.0 July 2016

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