AS4C64M32MD2-25BCN datasheet(35/129 Pages) ALSC

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4.6 Burst Terminate

The Burst Terminate (BST) command is initiated by having CS# LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3

LOW at the rising edge of clock. A Burst Teminate command may only be issued to terminate an active Read or Write

burst. Therefore, a Burst Terminate command may only be issued up to and including BL/2 - 1 clock cycles after a

Read or Write command. The effective burst length of a Read or Write command truncated by a BST command is as

follows: Effective burst length = 2 x {Number of clock cycles from the Read or Write Command to the BST command}

Note that if a read or write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the

truncated burst should be used as “BL” to calculate the minimum read to write or write to read delay.

The BST command only affects the most recent read or write command. The BST command truncates an ongoing

read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Burst Terminate command is

issued. The BST command truncates an ongoing write burst WL * tCK + tDQSS after the rising edge of the clock

where the Burst Terminate command is issued.

For LPDDR2-S4 devices, the 4-bit prefetch architecture allows the BST command to be issued on an even number of

clock cycles after a Write or Read command. Therefore, the effective burst length of Read or Write command

truncated by a BST command is an integer multiple of 4.

Figure 4.18 — LPDDR2-S4: Burst Write truncated by BST: WL = 1, BL = 16

NOTE 1 The BST command truncates an ongoing write burst WL * tCK + tDQSS after the rising edge of the clock where the

Burst Terminate command is issued.

NOTE 2 For LPDDR2-S4 devices, BST can only be issued an even number of clock cycles after the Write command.

NOTE 3 Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command.

Figure 4.19 — LPDDR2-S4: Burst Read truncated by BST: RL=3, BL = 16

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