PC87415VCG datasheet(4/42 Pages) NSC

4 / 42 page

40 Pin Description

41 PCI INTERFACE

Name

Type

Description

AD 310

MULTIPLEXED ADDRESS AND DATA

The direction of these pins are defined below

Phase

Target

Bus Master

Address Phase

Input

Output

Data Phase

-Read

Output

Input

-Write

Input

Output

CBE 30

COMMANDBYTE ENABLE

are multiplexed Bus commands and Byte enables

PAR

PARITY

is even parity across AD 310 and CBE 30 PAR is an input when AD 310 is an input it is an

output when AD 310 is an output

FRAME

CYCLE FRAME

is driven by the initiator to indicate the beginning and duration of an access

TRDY

TARGET READY

indicates that the current data phase of the transaction is ready to be completed

IRDY

INITIATOR READY

indicates that the inltiator is ready to complete the current data phase of the transaction

STOP

indicates that the current target is requesting the initiator to stop the current transaction

DEVSEL

DEVICE SELECT

when actively driven indicates the driving device has decoded its address as the target of

the current access

IDSEL

INITIALIZATION DEVICE SELECT

is used as a chip select during configuration read and write transactions

This input can be connected to one of the upper address lines AD 3111

PERR

PARITY ERROR

is used for reporting data parity errors during all PCI transactions except a Special Cycle

PERR

is an output when AD 310 and PAR are inputs it is an input when AD 310 and PAR are outputs

SERR

SYSTEM ERROR

is used for reporting address parity errors data parity errors on the Special Cycle

command or any other system error where the result will be catastrophic When reporting address parity

errors SERR

is an output

INTA

INTERRUPT

Interrupt request A

REQ

REQUEST

indicates to the bus arbiter that this device wants to use the bus and become a bus master

GNT

GRANT

indicates to this device that access to the bus has been granted

CLK

CLOCK

33 MHz PCI Clock

RST

RESET

PCI Reset

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