Rev. PrC | Page 8 of 13

Parameter

Test Conditions

Comment

Min

Typ

Max

Unit

IOVDD − DGND

2

3.6

V

I_IOVDD

CMOS clock, HR

7.5

mA

CMOS clock, LP

2.5

Power Dissipation

Reference Buffers PreQ,

VCM Enabled, Internal

reference Disabled, Osc

Enabled, SAR Disabled

HR

99

mW

LP

31.5

mW

Reference Buffers Off,

VCM Disabled, Internal

reference Disabled, Osc

Disabled, SAR Disabled

HR

85.5

mW

LP

27.5

mW

Power Down

All ADC’s disable

TBD

Μw

1

AVDDx = 3.3V, AVSSx = GND, IOVDD = 1.8V, CMOS clock

2

Disabling either VCM or Internal Reference would lead to a 40uA current consumption reduction

AD7771

Preliminary Technical Data