L9660 datasheet(28/49 Pages) STMICROELECTRONICS

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Functional description

L9660

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DocID024714 Rev 2

the state of the squib resistance is valid after THSR is captured on the next falling edge of

CS_D. The voltage source for this test is VBIAS which is based on the VDD supply.

A way to reduce the time required until valid results are available is to perform a leakage

diagnostics prior to this test. The leakage diagnostics biases the voltage on the squibs to

around 3.5V, which is the same bias voltage required for the high squib resistance

diagnostic. By running this sequence of diagnostics the test time reduces from 1.5ms to

200µs.

High and low side FET diagnostics

Prior to either the HS or LS FET diagnostics being run it is required to have the VRCM

switched ON. Running the leakage diagnostics with the appropriate delay time prior to either

the HS or LS FET diagnostics can do this. When the FET diagnostic command is issued the

flags is initially cleared. If the VRMC is not active or some leakage is present then the MOS

is not turned ON, the test is aborted and Fault Present (FP) bit set. The FEN function must

be inactive to run test. The test does not start if FEN function is active on channel under test

and it results in the Fault Present (FP) bit to set.

If no leakage is present and FEN function is inactive, the MOS (High side or Low Side) is

turned ON. The L9660 monitors the current sink or sourced by VRCM. If the MOS is working

properly, this current exceeds ISTB (HS test) or ISTG (LS test) and the L9660 turns off the

driver under test within the specified time TSHUTOFF. If the current does not exceed ISTB or

ISTG then the test is terminated and the MOS switched off by the L9660 within

TFETTIMEOUT. During the TFETTIMEOUT period the FET Time-out bit is set (FT=1) and cleared

at the expiration of the timer.

The results must be compared with the leakage diagnostic results to distinguish between a

real leakage/short versus a FET fault. For high side FET diagnostics if no faults were

indicated in the preceding leakage diagnostics then a normal result would be STB=1;STG=0

(with FT=0;FP=0). If the returned results for the high side FET test is not STB=1;STG=0

(with FT=0;FP=0) then either the FET is not functional, a short occurred during the test, or

there is a missing VRESx connection for that channel. For low side FET diagnostics if no

faults were indicated in the preceding leakage diagnostics then a normal result would be

STB=0;STG=1 (with FT=0;FP=0). If the returned results for the low side FET test is not

STB=0;STG=1 (with FT=0;FP=0) then either the FET is not functional, a short occurred

during the test, or there is a missing GNDx connection for that channel. If the test is in

progress then a bit (FT) is used in the response to indicate this status.

Once the command is issued, output of comparators is latched.

On the next falling edge of CS_D, comparator latched data is captured and reported to

MISO response. The results remain latched until the next test is initiated (diagnostic write

command). If the test is in progress then a bit is used in the response to indicate the test

completion. If the FET under test is working properly then the results indicate a “Short to

Ground” for LS test and “Short to Battery” for HS test. If a leakage is present prior to the test

or FENx is asserted then both “Short to Ground” and Short to Battery” are indicated in the

response for either a LS or HS FET test.

For all conditions the current on SQHx/SQLx never exceeds ISVRCM. On the squib lines there

may be higher transient currents due to the presence of the filter capacitor.

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