STW81200 datasheet(50/58 Pages) STMICROELECTRONICS

50 / 58 page

Circuit description

STW81200

50/58

DocID025943 Rev 7

7.16

Power ON sequence

In order to guarantee the correct start-up of the internal circuitry after the power on, the

following steps must be followed:

Power up the device (LDO supply pins: pin#9 #18, #28 and #36)

Once the voltages applied on the LDO supply pins are stable, wait 50 ms. (After this

transient time, the LDOs are powered on with the regulated voltages available at pins

#2, #8, #19, #27 and #29, while all other circuits are in power down mode)

Provide the reference clock signal

Implement the first programming sequence as follows:

Program register ST9 (test and initialization) with all bit set to ‘0’

Program register ST0 according to the desired configuration

Program the following registers in the specified order according to the desired

configuration: ST8, ST7, ST6, ST5, ST4, ST3, ST2, ST1, ST0

Check the PLL Lock status on pin LD_SDO (pin #26) and/or read all relevant

information provided on registers ST10 and ST11.

7.17

Example of Register programming

Setup conditions and requirements:

•

Unregulated Supply voltage: 5.0 V

•

Reference Clock: 122.88 MHz, single-ended, sine wave

•

LO Frequency: 2646.96 MHz – exact freq. mode (VCO Frequency=5293.92 MHz)

•

Output Power: +7 dBm (differential)

•

Phase Noise requirements: full performance VCO, full performance Noise floor.

•

ST9 = 0x48000000 (initialization; all bits set to ‘0’)

•

ST8 = 0x40000003 (REG_4V5 = 4.5 V)

•

ST7 = 0x39000000 (“fast lock” not used; LD_SDO pin configured as 2.5 V CMOS

buffer)

•

ST6 = 0x30001000 (DITHERING=0; DSM_ORDER=0 for 3rd order DSM;

CAL_TEMP_COMP=1 to guarantee lock on extreme temperature drift)

•

ST5 = 0x28000000 (low power modes not used)

•

ST4 = 0x2387838D (lock detector setting for fractional mode and FPFD = 61.44 MHz;

REF_BUF_MODE=3 for single-ended mode; VCO_AMP=15 for best VCO phase noise

@4.5 V supply; RF_OUT_PWR=7 to have +7 dBm differential)

•

ST3 = 0x18008002 (PFD_DEL_MODE = ‘VCO_DIV_delayed’, R=2 and

REF_PATH_SEL = 0 ‘direct’ for FPFD= 61.44 MHz)

•

ST2 = 0x13000080 (MOD=128; RF2_OUT_PD=1 for RF2 Output in power down)

•

ST1 = 0x08200015 (FRAC=21; RF1_DIVSEL=1 set RF1 Output with VCO freq.

Divided By 2)

•

ST0 = 0x03E00056 (NINT=86; PFD_DEL = 1.2 ns; CPSEL = 31 for Icp = 4.9 mA)

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