PC87334VLJ datasheet(94/102 Pages) NSC

부품명	PC87334VLJ

상세설명	SuperI/O 3.3V/5V Floppy Disk Controller, Dual UARTs, Infrared, IEEE1284 Parallel Port, and IDE Interface

PDF	102 Pages

Scroll/Zoom	100%

제조업체	NSC [National Semiconductor (TI)]

홈페이지	http://www.national.com

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94 / 102 page

100 Electrical Characteristics (Continued)

1038 DMA Timing

Symbol

Parameter

Min

Max

Units

tKI

FDACK or PDACK Inactive Pulse Width

tKK

FDACK or PDACK Active Pulse Width

tKQ

FDACK Active Edge to FDRQ Inactive (Note 1)

PDACK Active Edge to PDRQ Inactive (Note 1)

tQK

FDRQ to FDACK Active Edge

PDRQ to PDACK Active Edge

tQP

FDRQ Period (FDC-Burst DMA)

8 c tDRP

PDRQ Period (ECP)

330

tQQ

FDRQ or PDRQ Inactive Non-Burst Pulse Width

300

400

tQR

FDRQ to RD or WR Active

PDRQ to RD or WR Active

tQW

FDRQ to End of RD WR (Note 1)

(8 c tDRP) b (16 c tICP)

(FDRQ Service Time)

tQT

FDRQ to TC Active (Note 1)

(8 c tDRP) b (16 c tICP)

(FDRQ Service Time)

tRQ

RD WR Active Edge to FDRQ or PDRQ Inactive (Note 2)

tTQ

TC Active Edge to FDRQ or PDRQ Inactive

tTT

TC Active Pulse Width

Note 1

For FDC DMA Values shown are with the FIFO disabled or with FIFO enabled and THRESH e 0 For non-zero values of THRESH add (THRESH c 8 c

tDRP) to the values shown

For ECP DMA Value shown is with the FIFO disabled For FIFO enabled add (192 c TCP) to the value shown (assuming IOCHRDY e 1)

Note 2

The active edge of RD or WR and TC is recognized only when FDACK or PDACK is active

TLC12039 – 33

FIGURE 10-8 DMA Timing

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