ACE24C64BD

Two-wire Serial EEPROM

VER 1.1

6

Device Addressing

The 64K devices all require an 8-bit device address word following a start condition to enable the chip

for a read or write operation (see to Figure 4).

The device address word consists of a mandatory

“1”, “0” sequence for the first four most significant

bits as shown. This is common to all the EEPROM devices.

The next 3 bits are the A2, A1 and A0 device address bits for the 64K EEPROM. These 3 bits must

compare to their corresponding hard-wired input pins.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if

this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a

“0”. If a compare is not made, the

chip will return to a standby state.

Data Security: The ACE24C64BD has a hardware data protection scheme that allows the user to write

Write Operations

Byte Write:

A write operation requires an 8-bit data word address following the device address word and

acknowledgment. Upon receipt of this address, the EEPROM will again respond with a

“0” and then

clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a

“0”

and the addressing device, such as a microcontroller, must terminate the write sequence with a stop

All inputs are disabled during this write cycle and the EEPROM will not respond until the write is

complete (see to Figure 5).

Page Write:

A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition

after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data

word, the microcontroller can transmit up to 31 (64K) more data words. The EEPROM will respond with a

"0" after each data word received. The microcontroller must terminate the page write sequence with a

stop condition (see to Figure 6).

The data word address lower three (64K) bits are internally incremented following the receipt of each

data word. The higher data word address bits are not incremented, retaining the memory page row

location. When the word address, internally generated, reaches the page boundary, the following byte

is placed at the beginning of the same page. If more than 32 (64K) data words are transmitted to the

EEPROM,

the data word address will “roll over” and previous data will be overwritten.

Acknowledge Polling:

Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge

polling can be initiated. This involves sending a start condition followed by the device address word.

The read/write bit is representative of the operation desired. Only if the internal write cycle has

completed will the EEPROM respond with a

“0” allowing the read or write sequence to continue.