R5F104LEA datasheet(96/213 Pages) RENESAS

96 / 213 page

RL78/G14

2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85

°C)

R01DS0053EJ0330 Rev. 3.30

Page 96 of 208

Aug 12, 2016

Note 4.

This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.

Note 5.

Use it with EVDD0

≥ Vb.

Note 6.

The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer

rate.

Expression for calculating the transfer rate when 1.8 V

≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V

Note 7.

This value as an example is calculated when the conditions described in the “Conditions” column are met.

Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.

Caution

Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the 30- to 52-pin

products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the TxDq pin by using port input mode

input buffer selected.

(Remarks are listed on the next page.)

Maximum transfer rate =

[bps]

Baud rate error (theoretical value) =

Transfer rate

× 2

{-Cb

× Rb × In (1 -

)}

× 3

1.5

{-Cb

× Rb × In (1 -

)}

1.5

(

)

× Number of transferred bits

Transfer rate

× 100 [%]

* This value is the theoretical value of the relative difference between the transmission and reception sides.

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