R5F56519FDFP datasheet(9/190 Pages) RENESAS

9 / 190 page

RX65N Group, RX651 Group

1. Overview

R01DS0276EJ0100 Rev.1.00

Page 9 of 190

Aug 24, 2016

Note 1. Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc.

Note 2. The product part number differs according to whether or not it supports encryption.

Note 3. The product part number differs according to whether or not it includes an SDHI (SD host interface) / SDSI (SD slave interface).

Safety

Clock frequency

accuracy measurement

circuit (CAC)

 Monitors the clock output from the main clock oscillator, sub-clock oscillator, low- and

high-speed on-chip oscillators, the PLL frequency synthesizer, IWDT-dedicated on-chip

oscillator, and PCLKB, and generates interrupts when the setting range is exceeded.

Data operation circuit

(DOC)

 The function to compare, add, or subtract 16-bit data

Encryption

function

AESa*2

 Key lengths: 128, 192, and 256 bits

 Support for CFB, OFB, and CMAC operating modes

 Speed of calculations:

128-bit key length in 22 cycles

192-bit key length in 26 cycles

256-bit key length in 30 cycles

 Compliant with FIPS PUB 197

True random number

generator (RNGa)*2

 Length of random numbers: 16 bits

 Generation of random-number-generated interrupts after a number is generated

 Random number generation time: 1.9 ms (typ)

Operating frequency

Up to 120 MHz

Power supply voltage

VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7

 VREFH0  AVCC0,

VBATT = 2.0 to 3.6 V

Operating temperature

D-version:

40 to +85°C

G-version:

40 to +105°C (in planning)

Package

145-pin TFLGA (PTLG0145KA-A)

144-pin LFQFP (PLQP0144KA-B)

100-pin TFLGA (PTLG0100JA-A)

100-pin LFQFP (PLQP0100KB-B)

On-chip debugging system

 E1 emulator (JTAG and FINE interfaces)

 E20 emulator (JTAG interface)

Table 1.1

Outline of Specifications (8/8)

Classification

Module/Function

Description

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