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WM8524 데이터시트(PDF) 8 Page - Cirrus Logic |
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WM8524 데이터시트(HTML) 8 Page - Cirrus Logic |
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8 / 25 page ![]() WM8524 Production Data w PD, Rev 4.1, October 2011 8 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING Figure 1 System Clock Timing Requirements Test Conditions LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C PARAMETER SYMBOL MIN TYP MAX UNIT Master Clock Timing Information MCLK cycle time tMCLKY 27 500 ns MCLK high time tMCLKH 11 ns MCLK low time tMCLKL 11 ns MCLK duty cycle (tMCLKH/tMCLKL) 40:60 60:40 % |
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