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WM8912 데이터시트(PDF) 56 Page - Cirrus Logic

부품명 WM8912
상세설명  Ultra Low Power DAC with Headphone Driver
PDF  129 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8912 데이터시트(HTML) 56 Page - Cirrus Logic

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WM8912
Production Data
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PD, Rev 4.1, February 2013
56
Figure 32 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the 1
st (mode B) or 2nd (mode A) rising edge
of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 33 and Figure
34. In device slave mode, Figure 35 and Figure 36, it is possible to use any length of frame pulse less
than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before
the rising edge of the next frame pulse.
Figure 33 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master)
Figure 34 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master)



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