DLP2000 datasheet(25/40 Pages) TI1

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DLP2000

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DLPS078 – JULY 2017

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD: VSS, VCC, VOFFSET, VBIAS, and VRESET. DMD

power-up and power-down sequencing is strictly controlled by the DLPA1000 device.

VCC, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up and power-down

operations. Failure to meet any of the following requirements will result in a significant reduction in the DMD’s

reliability and lifetime. Refer to Figure 13.

CAUTION

For reliable operation of the DMD, the following power supply sequencing

requirements must be followed. Failure to adhere to the prescribed power-up and

power-down procedures may affect device reliability.

VCC, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-

up and power-down operations. Failure to meet any of the following requirements will

result in a significant reduction in the DMD’s reliability and lifetime.

9.1 Power Supply Power-Up Procedure

•

During Power-Up, VCC must always start and settle before VOFFSET, VBIAS, and VRESET voltages are applied to

the DMD.

•

During Power-Up, VBIAS does not have to start after VOFFSET. However, it is a strict requirement that the delta

between VBIAS and VOFFSET must be within ±8.75 V (Note 1).

•

During Power-Up, the DMD’s LVCMOS input pins shall not be driven high until after VCC has settled at

operating voltage.

•

During Power-Up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.

•

Slew Rates for Power-Up are flexible, as long as the transient voltage levels follow the requirements listed

previously.

9.2 Power Supply Power-Down Procedure

•

Power-Down sequence is the reverse order of the previous Power-Up sequence. VCC must be supplied until

after VBIAS, VRESET and VOFFSET are discharged to within 4 V of ground.

•

During Power-Down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement that

the delta between VBIAS and VOFFSET must be within ±8.75 V (Note 1).

•

During Power-Down, the DMD’s LVCMOS input pins must be less than VCC + 0.3 V.

•

During Power-Down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS.

•

Slew Rates for Power-Down are flexible, as long as the transient voltage levels follow the requirements listed

previously.

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