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CS61884 데이터시트(PDF) 59 Page - Cirrus Logic

부품명 CS61884
상세설명  Octal T1/E1/J1 Line Interface Unit
PDF  72 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS61884 데이터시트(HTML) 59 Page - Cirrus Logic

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CS61884
DS485PP4
59
19.7 Master Clock Switching Characteristics
19.8 Transmit Switching Characteristics
19.9 Receive Switching Characteristics
* All parameters guaranteed by production, characterization or design.
Notes: 20. Output load capacitance = 50pF.
21. MCLK is not active.
22. Parameters guaranteed by design and characterization.
Parameter
Symbol
Min.
Typ
Max
Units
MASTER CLOCK (MCLK)
Master Clock Frequency
E1 Modes
MCLK
2.048
MHz
Master Clock Frequency
T1/J1 Modes
MCLK
1.544
MHz
Master Clock Tolerance
-
-100
+100
ppm
Master Clock Duty Cycle
-
40
50
60
%
Parameter
Symbol
Min.
Typ
Max
Units
E1 TCLK Frequency
1/tpw2
-
2.048
-
MHz
E1 TPOS/TNEG Pulse Width (RZ Mode)
236
244
252
nS
T1/J1 TCLK Frequency
1/tpw2
-
1.544
-
MHz
TCLK Tolerance (NRZ Mode)
-50
-
50
PPM
TCLK Duty Cycle
tpwh2/tpw2
--
90
%
TCLK Pulse Width
20
-
-
nS
TCLK Burst Rate
Note 22
--
20
MHz
TPOS/TNEG to TCLK Falling Setup Time (NRZ Mode)
tsu2
25
-
-
nS
TCLK Falling to TPOS/TNEG Hold time (NRZ Mode)
th2
25
-
-
nS
TXOE Asserted Low to TX Driver HIGH-Z
-
-
1
µS
TCLK Held Low to Driver HIGH-Z
Note 21
812
20
µS
Parameter
Symbol
Min.
Typ
Max
Units
RCLK Duty Cycle
40
50
60
%
E1 RCLK Pulse Width
196
244
328
nS
E1 RPOS/RNEG Pulse Width (RZ Mode
200
244
300
nS
E1 RPOS/RNEG to RCLK rising setup time
tsu
150
244
-
nS
E1 RPOS/RNEG to RCLK hold time
th
200
244
-
nS
T1/J1 RCLK Pulse Width
259
324
388
nS
T1/J1 RPOS/RNEG Pulse Width (RZ Mode)
250
324
400
nS
T1/J1 POS/RNEG to RCLK rising setup time
tsu
150
324
-
nS
T1/J1 RPOS/RNEG to RCLK hold time
th
200
324
-
nS
RPOS/RNEG Output to RCLK Output (RZ Mode)
-
-
10
nS
Rise/Fall Time, RPOS, RNEG, RCLK, LOS outputs
tr,tf
-
-
85
nS



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