520 - 64 - 7

13

shown in Figure 12. The pipelined output section of the 48

tap filter is shown in Figure 14. Note that two register delays

are introduced due to R2 and R3 between the accumulators

of device number 1 and number 2. An additional delay is

introduced when the filter-sum is fed back to be added to

the next sum by selecting FB_SEL_1. The timing diagram

for the 48 tap asymmetric filter is shown in Figure 15. The

processing clock runs at twice the data rate since the A and

B registers of the GF9101 are multiplexed internally..

TABLE 11 Configuration Word for the Cascaded GF9101’s

DEVICE NO. 1

DEVICE NO. 2

BIT NO.

CONFIG.

WORD

CONFIG.

WORD

DESCRIPTION

0

1

1

Data A and B are both signed data.

11

1

2

0

0

1 clock cycle delay in device no. 1 and 4 clock delay in device no. 2

30

1

4

0

0

Using each device as 2 x 12 tap filters. Note that in device no. 2

DATA_A_OUT is externally connected to DATA_B_IN.

5

0

0

Assuming serial load mode selected for both devices.

60

0