AD9684 datasheet(11/65 Pages) AD

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AD9684

Data Sheet

Rev. 0 | Page 10 of 64

CLK+

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

SYNC+

APERTURE DELAY

N + x

N + 36

N + 37

N + 38

D13±

D0±

CONVERTER 0

SAMPLE

[N]

VIN±x

STATUS

D13

CLK–

SYNC–

STATUS+

(OVERRANGE/STATUS BIT)

STATUS–

tCLK

tDCO

CONSTANT LATENCY = X CLK CYCLES

tPD

tSKEWF

tSKEWR

CONVERTER 1

SAMPLE

[N]

CONVERTER 0

SAMPLE

[N + 1]

CONVERTER 1

SAMPLE

[N + 1]

CONVERTER 0

SAMPLE

[N + 2]

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

STATUS BIT SELECTED BY

IN THE REGISTER MAP

D13

Figure 5. Parallel Interleaved Mode—Two Converters, ≤14-Bit Data, Output Sample Rate < 625 MSPS

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