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ICS8735AM-21 데이터시트(PDF) 8 Page - List of Unclassifed Manufacturers

부품명 ICS8735AM-21
상세설명  700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
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ICS8735AM-21
www.icst.com/products/hiperclocks.html
REV. D OCTOBER 27, 2003
8
Integrated
Circuit
Systems, Inc.
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 3B. LVPECL OUTPUT TERMINATION
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 4. ICS8735-21 LVPECL BUFFER SCHEMATIC EXAMPLE
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of the ICS8735-21. In this
example, the input is driven by an HCSL driver. The zero delay
buffer is configured to operate at 155.52MHz input and 77.75MHz
output. The logic control pins are configured as follows:
SEL [3:0] = 0101; PLL_SEL = 1
The decoupling capacitors should be physically located near the
power pin. For ICS8735-21.
R7
10
3.3V
SP = Space (i.e. not intstalled)
Zo = 50 Ohm
RU3
1K
SEL3
VCC
SEL1
C1
0.1uF
Bypass capacitors located
near the power pins
R8
50
VCCA
SEL3
C11
0.01u
VCCA
R1
50
VCC
(155.5 MHz)
VCC
SEL[3:0] = 0101,
Divide by 2
VCC
SEL0
RU7
SP
C2
0.1uF
SEL2
VCC
SEL0
SEL2
RD6
SP
(77.75 MHz)
RD7
1K
R9
50
(U1-4) VCC
RU4
1K
R6
50
RD4
SP
Zo = 50 Ohm
Zo = 50 Ohm
R4
50
RU5
SP
LVPECL_input
+
-
(U1-13)
PLL_SEL
R5
50
(U1-17)
HCSL
R2
50
SEL1
Zo = 50 Ohm
RD3
SP
U1
ICS8735-21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
CLK
nCLK
MR
VCCI
nFB_IN
FB_IN
SEL2
VEE
nQFB
QFB
nQ
Q
VCCO
SEL3
VCCA
PLL_SEL
nc
SEL1
SEL0
VCCI
C3
0.1uF
VCC=3.3V
R3
50
RD5
1K
C16
10u
RU6
1K
PLL_SEL



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