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ICS8735AM-21 데이터시트(PDF) 1 Page - List of Unclassifed Manufacturers

부품명 ICS8735AM-21
상세설명  700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
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8735AM-21
www.icst.com/products/hiperclocks.html
REV. D OCTOBER 27, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8735-21 is a highly versatile 1:1 Differ-
ential-to-3.3V LVPECL clock generator and a
member of the HiPerClockS™family of High Per-
formance Clock Solutions from ICS. The CLK,
nCLK pair can accept most standard differential
input levels. The ICS8735-21 has a fully integrated PLL and
can be configured as zero delay buffer, multiplier or divider,
and has an output frequency range of 31.25MHz to 700MHz.
The reference divider, feedback divider and output divider
are each programmable, thereby allowing for the following out-
put-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.
The external feedback allows the device to achieve “zero
delay” between the input clock and the output clocks. The
PLL_SEL pin can be used to bypass the PLL for system test
and debug purposes. In bypass mode, the reference clock
is routed around the PLL and into the internal output dividers.
FEATURES
• 1 differential 3.3V LVPECL output pair,
1 differential feedback output pair
• Differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Cycle-to-cycle jitter: 25ps (maximum)
• Static phase offset: 50ps ± 100ps
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
HiPerClockS™
ICS
BLOCK DIAGRAM
PIN ASSIGNMENT
ICS8735-21
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
CLK
nCLK
MR
VCC
nFB_IN
FB_IN
SEL2
VEE
nQFB
QFB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
SEL1
SEL0
VCC
PLL_SEL
VCCA
SEL3
VCCO
Q
nQ
PLL_SEL
CLK
nCLK
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q
nQ
QFB
nQFB
0
1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64


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