ST92F120 datasheet(96/324 Pages) STMICROELECTRONICS

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ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)

7.3 CLOCK MANAGEMENT

The various programmable features and operating modes of the CCU are handled by four registers:

– MODER (Mode Register)

This is a System Register (R235, Group E).

The input clock divide-by-two and the CPU clock

prescaler factors are handled by this register.

– CLKCTL (Clock Control Register)

This is a Paged Register (R240, Page 55).

The low power modes and the interpretation of

the HALT instruction are handled by this register.

– CLK_FLAG (Clock Flag Register)

This is a Paged Register (R242, Page 55).

This register contains various status flags, as

well as control bits for clock selection.

– PLLCONF (PLL Configuration Register)

This is a Paged Register (R246, Page 55).

The PLL multiplication and division factors are

programmed in this register.

Figure 44. Clock Control Unit Programming

Quartz

PLL

CK_AF

1/16

1/2

DIV2

CKAF_SEL

1/N

oscillator

MX(1:0)

source

CKAF_ST

CSU_CKSEL

6/8/10/14

XT_DIV16

DX(2:0)

CLOCK2

CLOCK1

(MODER)

(CLK_FLAG)

(CLKCTL)

(PLLCONF)

(CLK_FLAG)

CK_AF

INTCLK

Peripherals

CPU Clock Prescaler

XTSTOP

(CLK_FLAG)

Wait for Interrupt and Low Power Modes:

LPOWFI (CLKCTL) selects Low Power operation automatically on entering WFI mode.

WFI_CKSEL (CLKCTL) selects the CK_AF clock automatically, if present, on entering WFI mode.

XTSTOP (CLK_FLAG) automatically stops the Xtal oscillator when the CK_AF clock is present and selected.

and P6.5

1/4

CLK_128

(available only if mapped on ext. pin)

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