Revision 1.1

Jun. 7, 1999

-17-

GL640USB, GL640USB-A

R/W

R/W

R/W

R/W

EP3STL

EP2STL

EP1STL

EP0STL

Default=8’h00

EPnSTL

-

Endpoint n is stalled

By setting EPnSTL to ‘1’, endpoint n will respond with a STALL to incoming

USB packet.

GPI (offset 92h)

R/O

R/O

R/O

GPI3

GPI2

GPI1

INTFLG ( offset 93h )

R/O

R/W1C

R/W1C

R/W1C

R/O

R/O

R/W1C

R/W1C

Reserved

RESUME

SUSPND

EPPINT

Reserved

EP3TX

DATARX

DATATX

Default=8’h00

This register is used to identify the exact interrupt event. When the external controller receives an interrupt, it

should first read this register to check the interrupt event. Writing ‘1’ to clear the individual interrupt bit.

DATATX -

The endp1 transmits a data packet completely

DATARX -

The endp2 receives a data packet

EP3TX

-

Endp3 transaction is detected

EPPINT

-This bit means external EPP interrupt is detected.

The EPPTXEN/EPPRXEN is cleared by hardware when this bit is set.

SUSPND

-

USB suspend request is detected.

RESUME -

USB resume request is detected.

UINTEN ( offset 94h )

R/W

R/W

R/W

R/W

R/O

R/W

R/W

R/W

FFINT

REMINT

SUSINT

DMAINT

Reserved

UINTEN

DRXINT

DTXINT

These are the interrupt enable bits of INTFLG register.

Default = 8’h00

USBFLG ( offset 95h )

R/W1C

R/O

R/O