AD9993BBCZ datasheet(32/57 Pages) AD

32 / 57 page

Data Sheet

AD9993

Rev. A | Page 31 of 56

CHIP GRADE REGISTER

Address: 0x002, Reset: 0x01, Name: CHIP_GRADE

Table 13. Bit Descriptions for CHIP_GRADE

Bits

Bit Name

Description

Reset

Access

[5:4]

CHIP_SPEED_GRADE

Chip ID/speed grade.

0x0

[2:0]

CHIP_DIE_REV

Chip die revision.

0x1

DEVICE INDEX REGISTER

Address: 0x005, Reset: 0x0F, Name: DEVICE_INDEX

Table 14. Bit Descriptions for DEVICE_INDEX

Bits

Bit Name

Description

Reset

Access

SPI_ADC_D_INDEX

ADC Core D access enable.

0x1

1 = ADC Core D receives the next read/write access from the SPI interface.

0 = ADC Core D does not receive the next read/write access from the SPI

interface.

SPI_ADC_C_INDEX

ADC Core C access enable.

0x1

1 = ADC Core C receives the next read/write access from the SPI interface.

0 = ADC Core C does not receive the next read/write access from the SPI

interface.

SPI_ADC_B_INDEX

ADC Core B access enable.

0x1

1 = ADC Core B receives the next read/write access from the SPI interface.

0 = ADC Core B does not receive the next read/write access from the SPI

interface.

SPI_ADC_A_INDEX

ADC Core A access enable.

0x1

1 = ADC Core A receives the next read/write access from the SPI interface.

0 = ADC Core A does not receive the next read/write access from the SPI

interface.

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