AD9993BBCZ datasheet(23/57 Pages) AD

23 / 57 page

AD9993

Data Sheet

Rev. A | Page 22 of 56

Figure 27. Output Sample Data Format

Figure 28. DAC Input Sample Data Format

LVDS INTERFACE TIMING

DAC Input Interface

Table 8 specifies the setup and hold time requirements for DAC

LVDS data lane inputs relative to DCI. Figure 29 shows a timing

diagram for this interface. DDR DCI edges occur at the position

within the data eye (the white region in Figure 29) listed in

Table 8.

Table 8. DAC DDR LVDS Input Setup and Hold Times

Relative to DCI (Guaranteed)

Parameter

Minimum

Unit

|tSU|

150

|tHOLD|

200

Data Period

1000

Figure 29. DAC Input LVDS Lane Timing

ADC Output Interface

Figure 30. ADC Output LVDS Lane Timing

DCO_P

ADC LVDS

A/B/C/D

(DATA CLOCK OUTPUT PORT)

LANE 3

STROBE+

LANE 2

LANE 1

LANE 0

D[–2]

(SAMPLE N – 1)

D[–1]

(SAMPLE N)

D[–2]

(SAMPLE N)

OVERRANGE

(SAMPLE N + 1)

D[2]

(SAMPLE N – 1)

D[5]

(SAMPLE N)

D[8]

(SAMPLE N)

D[1]

(SAMPLE N – 1)

D[4]

(SAMPLE N)

D[7]

(SAMPLE N)

D[0]

(SAMPLE N – 1)

D[3]

(SAMPLE N)

D[2]

(SAMPLE N)

D[1]

(SAMPLE N)

D[0]

(SAMPLE N)

D[11]

(SAMPLE N + 1)

D[10]

(SAMPLE N + 1)

D[9]

(SAMPLE N + 1)

D[6]

(SAMPLE N)

OVERRANGE

(SAMPLE N)

D[11]

(SAMPLE N)

D[10]

(SAMPLE N)

D[9]

(SAMPLE N)

LANE 6

LANE 5

LANE 4

LANE 3

LANE 2

LANE 1

LANE 0

DCI_P

(DATA CLOCK INPUT PORT)

D[6]

(SAMPLE N – 1)

D[5]

(SAMPLE N – 1)

D[4]

(SAMPLE N – 1)

D[3]

(SAMPLE N – 1)

D[2]

(SAMPLE N – 1)

D[1]

(SAMPLE N – 1)

D[0]

(SAMPLE N – 1)

D[6]

(SAMPLE N + 1)

D[5]

(SAMPLE N + 1)

D[4]

(SAMPLE N + 1)

D[3]

(SAMPLE N + 1)

D[2]

(SAMPLE N + 1)

D[1]

(SAMPLE N + 1)

D[0]

(SAMPLE N + 1)

D[6]

(SAMPLE N)

D[5]

(SAMPLE N)

D[4]

(SAMPLE N)

D[3]

(SAMPLE N)

D[2]

(SAMPLE N)

D[1]

(SAMPLE N)

D[0]

(SAMPLE N)

D[13]

(SAMPLE N)

D[12]

(SAMPLE N)

D[11]

(SAMPLE N)

D[10]

(SAMPLE N)

D[9]

(SAMPLE N)

D[8]

(SAMPLE N)

D[7]

(SAMPLE N)

D[13]

(SAMPLE N + 1)

D[12]

(SAMPLE N + 1)

D[11]

(SAMPLE N + 1)

D[10]

(SAMPLE N + 1)

D[9]

(SAMPLE N + 1)

D[8]

(SAMPLE N + 1)

D[7]

(SAMPLE N + 1)

D[13]

(SAMPLE N + 2)

D[12]

(SAMPLE N + 2)

D[11]

(SAMPLE N + 2)

D[10]

(SAMPLE N + 2)

D[9]

(SAMPLE N + 2)

D[8]

(SAMPLE N + 2)

D[7]

(SAMPLE N + 2)

DATA PERIOD

tSU tHOLD

DATA PERIOD

DATA

CLOCK

DATA

PERIOD

DATA

PERIOD

STROBE_P/

STROBE_N

DCO_P/

DCO_N

DATA

tSU tHOLD

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