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DAC7632 데이터시트(PDF) 12 Page - Burr-Brown (TI) |
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DAC7632 데이터시트(HTML) 12 Page - Burr-Brown (TI) |
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12 / 21 page ![]() DAC7632 12 SBAS234 www.ti.com FIGURE 1. DAC7632 Architecture. R 2R 2R 2R 2R 2R 2R 2R 2R 2R V REFH V OUT V OUT Sense V REFH Sense V REFL V REFL Sense R F TYPICAL CHARACTERISTICS: VSS = –5V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. Time (1 µs/div) OUTPUT VOLTAGE vs MID-SCALE GLITCH PERFORMANCE +5V LDAC 0 7FFF H to 8000H Time (1 µs/div) OUTPUT VOLTAGE vs MID-SCALE GLITCH PERFORMANCE +5V LDAC 0 8000 H to 7FFFH THEORY OF OPERATION The DAC7632 is a dual channel, voltage output, 16-bit DAC. The architecture is an R-2R ladder configuration with the three MSB’s segmented, followed by an operational amplifier that serves as a buffer. Each DAC has its own R-2R ladder network, segmented MSBs, and output op amp, as shown in Figure 1. The minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by the external voltage references VREFL and VREFH, respectively. The digital input is a 24-bit serial word that contains an address bit for selecting one of two DACs, a quick load bit, six unused bits, and the 16-bit DAC code (MSB first). The converters can be powered from either a single +5V supply or a dual ±5V supply. The device offers a reset function which immediately sets all DAC output voltages, DAC regis- ters and input registers to mid-scale (code 8000H) or to zero- scale (code 0000H), depending on the state of RSTSEL. See Figures 2 and 3 for the basic configurations of the DAC7632. |
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