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DAC7632 데이터시트(PDF) 16 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
부품명 DAC7632
상세설명  16-Bit, Dual Voltage Output DIGITAL-TO-ANALOG CONVERTER
PDF  21 Pages
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제조업체  BURR-BROWN [Burr-Brown (TI)]
홈페이지  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

DAC7632 데이터시트(HTML) 16 Page - Burr-Brown (TI)

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DAC7632
16
SBAS234
www.ti.com
FIGURE 11. Linearity and Differential Linearity Error Charac-
teristic Curves for Figure 10.
FIGURE 12. Low-Cost Single-Supply Configuration.
FIGURE 13. Linearity and Differential Linearity Error Charac-
teristic Curves for Figure 12.
V
OUTA
V
OUTA Sense
V
REFL Sense
V
REFL
V
REFH
V
REFH Sense
V
OUTB Sense
V
OUTB
32
31
30
29
28
27
26
25
DAC7632
V
OUT
V
OUT
+2.5V
+V
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H C000H
E000
H FFFFH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
°C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H C000H
E000
H FFFFH
FIGURE 10. Single-Supply Buffered VREFH.
V
OUTA
V
OUTA Sense
V
REFL Sense
V
REFL
V
REFH
V
REFH Sense
V
OUTB Sense
V
OUTB
32
31
30
29
28
27
26
25
DAC7632
V
OUT
V
OUT
+V
OPA2350
+2.5V
+V
1000pF
100
Ω
2200pF
DIGITAL INTERFACE
See Table I for the basic control logic for the DAC7632. The
interface consists of a Serial Data Clock (CLK) input, Serial
Data Input (SDI), Input Register Load Control Signal (LOAD),
and DAC Register Load Control Signal (LDAC). In addition, a
Chip Select (CS ) input is available to enable serial communi-
cation when there are multiple serial devices attached to a
single serial bus. An asynchronous Reset (RST) input (rising
edge triggered) is provided to simplify start-up conditions,
periodic resets, or emergency resets to a known state, de-
pending on the status of the Reset Select (RSTSEL) signal.
The DAC code, quick load control, and address are provided
via a 24-bit serial interface (see Figure 15). The first bit
(DACSEL) selects the input register that will be updated
when LOAD goes LOW. The third bit is a “Quick Load” bit
such that if HIGH, the code in the shift register is loaded into
both input registers when the LOAD signal goes LOW. If the
“Quick Load” bit is LOW when an active LOAD signal is
issued, the content of the shift register is loaded only to the
input register that is addressed by DACSEL. The “Quick
Load” bit is followed by five unused bits. The last 16 bits
(MSB first) make up the DAC code.



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