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AR0130CSSC00SPBA0-DP1 데이터시트(PDF) 34 Page - ON Semiconductor

부품명 AR0130CSSC00SPBA0-DP1
상세설명  1/3?릋nch CMOS Digital Image Sensor
PDF  39 Pages
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
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34
POWER-ON RESET AND STANDBY TIMING
Power-Up Sequence
The recommended power-up sequence for the AR0130 is
shown in Figure 31. The available power supplies (VDD_IO,
VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have
the separation specified below.
1. Turn on VDD_PLL power supply.
2. After 0−10
ms, turn on VAA and VAA_PIX power
supply.
3. After 0−10
ms, turn on VDD power supply.
4. After 0−10
ms, turn on VDD_IO power supply.
5. After the last power supply is stable, enable
EXTCLK.
6. Assert RESET_BAR for at least 1 ms.
7. Wait 150,000 EXTCLKs (for internal initialization
into software standby).
8. Configure PLL, output, and image settings to
desired values.
9. Wait 1 ms for the PLL to lock.
10. Set streaming mode (R0x301a[2] = 1).
Figure 31. Power Up
EXTCLK
VDD_SLVS
VAA_PIX
VAA (2.8)
VDD_IO (1.8/2.8)
VDD (1.8)
VDD_PLL (2.8)
t0
t1
t2
t3
t4
t5
t6
tX
Hard
Reset
Internal Ini-
tialization
Software
Standby
PLL Clock
Streaming
RESET_BAR
Table 19. POWER-UP SEQUENCE
Symbol
Definition
Min
Typ
Max
Unit
t0
VDD_PLL to VAA/VAA_PIX (Note 20)
0
10
–
ms
t1
VAA/VAA_PIX to VDD
0
10
–
ms
t2
VDD to VDD_IO
0 (Note 21)
10
–
ms
t3
VDD_IO to VDD_SLVS
0
10
–
ms
tX
Xtal Settle Time
–
30 (Note 18)
–
ms
t4
Hard Reset
1 (Note 19)
–
–
ms
t5
Internal Initialization
150,000
–
–
EXTCLKs
t6
PLL Lock Time
1
–
–
ms
18.Xtal settling time is component-dependent, usually taking about 10–100 ms.
19.Hard reset time is the minimum time required after power rails are settled. In a circuit where hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
20.It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
others. If the case happens that VDD_PLL is powered after other supplies then the sensor may have functionality issues and will experience
high current draw on this supply.
21.For the case where VDD_IO is 2.8 V and VDD is 1.8 V, it is recommended that the minimum time be 5 ms.



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