AR0230CS

www.onsemi.com

4

SLVS0_P

SLVS0_N

SLVS1_P

SLVS1_N

SLVS2_N

SLVS2_P

SLVS3_P

SLVS3_N

SLVSC_P

SLVSC_N

FLASH

SHUTTER

SCLK

TRIGGER

OE_BAR

TEST

EXTCLK

From

controller

Master clock

(6−48 MHz)

Digital

I/O

power

!

Digital

Core

power

!

HiSPi

power

!

PLL

power

!

Analog

power

!

Analog

power

!

RESET_BAR

Digital

ground

Analog

ground

To

controller

NOTES:

1. All power supplies must be adequately decoupled

2. ON Semiconductor recommends a resistor value of 1.5k

Ω, but a greater value may be used for

slower two−wired speed.

3. The parallel interface output pads can be left unconnected if the serial output interface is used.

4. ON Semiconductor recommends that 0.1

μF and 10 μF decoupling capacitors for each power

supply are mounted as close as possible to the pad. Actual values and results may vary

depending on lay out and design considerations. Refer to the AR0230CS demo headboard

schematics for circuit recommendations.

5. ON Semiconductor recommends that analog power planes are placed in a manner such that

coupling with the digital power planes is minimized.

currents.

Figure 2. Typical Configuration: Serial Four−Lane HiSPi Interface