5

PS8689B

08/05/04

PI6CU877

PLL Clock Driver for

1.8V DDR2 Memory

Symbol

Decription

Units

Min.

Max.

FCK

25

300

MHz

160

270

Input clock duty cycle

40

60

%

15

µs

8

ns

Notes:

7.

The PLL is able to handle spread spectrum induced skew.

8.

Operating clock frequency indicates a range over which the PLL is able to lock, but in which it is not required to meet the other

timing parameters. (Used for low-speed debug).

9.

Application clock frequency indicates a range over which the PLL must meet all timing parameters.

10. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference

signal after power up . During normal operation, the stabilization time is also the time required for the integrated PLL circuit to

obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down

mode and later return to active operation. CK and CK maybe left floating after they have been driven low for one complete clock cycle.

DC Specifications

Param-

eter

Description

Test Condition

Min.

Typ.

Max.

Units

All Inputs

1.7V

1.2

V

HIGH output voltage

1.7 to

1.9V

-0.2

1.7

1.1

Output disabled low current

1.7V

100

µA

Output differenital voltage, the magniture of the difference

between the true and complimentary outputs, see fig. 9 for

dimentions

0.6

V

CK, CK

1.9V

±250

µA

±10

500

tion

CK and CK = 270MHz,

all outputs are open (not

connected to a PCB)

300

mA

CI

CK, CK

1.8V

2

3

pF

2

3

CI(∆)

CK, CK

0.25

0.25

Notes:

6.