HT86XXX

Rev. 1.70

21

May 6, 2004

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] and [02H] accesses the RAM pointed to

by MP0 (01H) and MP1 (03H) respectively. Reading lo-

cation 00H or 02H indirectly returns the result 00H.

While, writing it indirectly leads to no operation.

The function of data movement between two indirect ad-

dressing registers is not supported. The memory pointer

registers, MP0 and MP1, are both 8-bit registers used to

access the RAM by combining the corresponding indi-

rect addressing registers.

Accumulator

- ACC (05H)

The accumulator (ACC) is related to the ALU opera-

tions. It is also mapped to location 05H of the RAM and

is capable of operating with immediate data. The data

movement between two data memory locations must

pass through the ACC.

Arithmetic and Logic Unit

- ALU

This circuit performs 8-bit arithmetic and logic opera-

tions and provides the following functions:

Status Register

- STATUS (0AH)

This 8-bit STATUS register (0AH) consists of a zero flag

(Z), carry flag (C), auxiliary carry flag (AC), overflow flag

(OV), power down flag (PD), watchdog time-out flag

(TO). It also records the status information and controls

the operation sequence.

Except the TO and PD flags, bits in the status register

can be altered by instructions similar to other registers.

Data written into the status register does not alter the TO

or PD flags. Operations related to the status register,

however, may yield different results from those in-

tended. The TO and PD flags can only be changed by a

Watchdog Timer overflow, chip power-up, or clearing

the Watchdog Timer and executing the

²HALT² instruc-

tion. The Z, OV, AC, and C flags reflect the status of the

latest operations.

On entering the interrupt sequence or executing the

subroutine call, the status register will not be automati-

cally pushed onto the stack. If the contents of the status

is important, and if the subroutine is likely to corrupt the

status register, the programmer should take precautions

and save it properly.

Interrupts

The HT86XXX provides an external interrupt, three

16-bit programmable timer interrupts, and an 8-bit pro-

grammable timer interrupt. The Interrupt Control regis-

ters (INTC:0BH, INTCH:1EH) contain the interrupt

control bits to set to enable/disable and the interrupt re-

quest flags.

Once an interrupt subroutine is serviced, all other inter-

rupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may happen during this interval but

only the interrupt request flag is recorded. If a certain in-

terrupt needs servicing within the service routine, the

EMI bit and the corresponding INTC/INTCH bit may be

set to allow interrupt nesting. If the stack is full, the inter-

rupt request will not be acknowledged, even if the re-

lated interrupt is enabled, until the SP is decremented. If

immediate service is desired, the stack must be pre-

vented from becoming full.

Labels

Bits

Function

C

0

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

AC

1

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the

high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z

2

Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

OV

3

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

PD

4

PD is cleared by system power-up or executing the

²CLR WDT² instruction. PD is set by exe-

cuting the

²HALT² instruction.

TO

5

TO is cleared by system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

¾

6, 7

Unused bit, read as

²0²

Status Register