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전자부품 데이터시트 검색엔진 |
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Hello, Please ask a question about SN65CML100 Datasheet
# Example questions:
➢ What is the typical maximum propagation delay (tphl) specified for the sn65cml100, and under what termination conditions is this value applicable?
➢ What is the function of the vbb pin on the sn65cml100, and what type of signal does it provide?
➢ What input voltage conditions result in a high output signal (h) for the sn65cml100 receiver?
| Part No. | SN65CML100 |
| Manufacturer | TI |
| Size | 164 Kbytes |
| Pages | 15 pages |
| Description | 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER |
# SN65CML100 1.5-Gbps LVDS/LVPECL/CML Translator/Repeater
## Features
️· Level translation from LVDS/LVPECL to CML, repeating CML to CML.
️· Signaling rates up to 1.5 Gbps.
️· Compatible with 3.3V, 2.5V, or 1.8V supplies.
️· Total jitter < 70 ps.
️· Low 100 ps part-to-part skew.
️· Wide common-mode receiver capability.
️· 25 mV receiver input hysteresis.
️· 800 ps maximum propagation delay.
️· Available in SOIC and MSOP packages.
## Applications
️· Level translation.
️· 622 MHz central office clock distribution.
️· High-speed network routing.
️· Wireless basestations.
️· Low jitter clock repeater.
## Description
This translator/repeater supports signaling rates up to 1.5 Gbps for high-speed network routing. The CML-compatible output drives 50Ω or 25Ω loads connected to 1.8V, 2.5V, or 3.3V supplies. It's compatible with LVDS, LVPECL and CML signaling. The receiver tolerates a wide common-mode voltage range.
## Electrical Characteristics
️· Supply Voltage: 3.3V (range: 3 – 3.6V)
️· Input Voltage: 0-4V
️· Output Voltage: Compatible with VTT (1.7V, 2.5V, 3.3V)
️· Propagation Delay: 800ps maximum
️· Jitter: < 70ps
## Package Options
️· SOIC
️· MSOP
# SN65CML100 1.5-Gbps LVDS/LVPECL/CML Translator/Repeater
## Features
️· Level translation from LVDS/LVPECL to CML, repeating CML to CML.
️· Signaling rates up to 1.5 Gbps.
️· Compatible with 3.3V, 2.5V, or 1.8V supplies.
️· Total jitter < 70 ps.
️· Low 100 ps part-to-part skew.
️· Wide common-mode receiver capability.
️· 25 mV receiver input hysteresis.
️· 800 ps maximum propagation delay.
️· Available in SOIC and MSOP packages.
## Applications
️· Level translation.
️· 622 MHz central office clock distribution.
️· High-speed network routing.
️· Wireless basestations.
️· Low jitter clock repeater.
## Description
This translator/repeater supports signaling rates up to 1.5 Gbps for high-speed network routing. The CML-compatible output drives 50Ω or 25Ω loads connected to 1.8V, 2.5V, or 3.3V supplies. It's compatible with LVDS, LVPECL and CML signaling. The receiver tolerates a wide common-mode voltage range.
## Electrical Characteristics
️· Supply Voltage: 3.3V (range: 3 – 3.6V)
️· Input Voltage: 0-4V
️· Output Voltage: Compatible with VTT (1.7V, 2.5V, 3.3V)
️· Propagation Delay: 800ps maximum
️· Jitter: < 70ps
## Package Options
️· SOIC
️· MSOP
| Part No. | SN65CML100 |
| Manufacturer | TI |
| Size | 164 Kbytes |
| Pages | 15 pages |
| Description | 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER |
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