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SN65CML100 데이터시트(PDF) 1 Page - Texas Instruments |
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SN65CML100 데이터시트(HTML) 1 Page - Texas Instruments |
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1 / 15 page ![]() SN65CML100 SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES D Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML D Signaling Rates1 up to 1.5 Gbps D CML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V Supplies D Total Jitter < 70 ps D Low 100 ps (Max) Part-To-Part Skew D Wide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals D 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range D Propagation Delay Times, 800 ps Maximum D 3.3-V Supply Operation D Available in SOIC and MSOP Packages APPLICATIONS D Level Translation D 622-MHz Central Office Clock Distribution D High-Speed Network Routing D Wireless Basestations D Low Jitter Clock Repeater DESCRIPTION This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50- Ω or 25-Ω loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA–644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion. The VBB pin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBB as a switching reference voltage. When used, decouple VBB with a 0.01- µF capacitor and limit the current sourcing or sinking to 400 µA. When not used, VBB should be left open. This device is characterized for operation from –40 °C to 85 °C. FUNCTIONAL DIAGRAM 8 2 3 4 7 6 VCC A B VBB Y Z EYE PATTERN 1.5 Gbps 223–1 PRBS 750 MHz VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 3.3 V, RT = 50 Ω Vertical Scale = 500 mV/div Horizontal Scale = 200 ps/div PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 1The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. www.ti.com Copyright 2002, Texas Instruments Incorporated |
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